The Women Essay Example | Topics and Well Written Essays - 500 words

The Women - Essay Example She begins to critically examine her life and her relationship with men and the people around her. At some point, she considered divorce, and this would have not only affected her but also their daughter. This play thus helps to remind the audience that although one might appear to lead a happy and comfortable life, problems in marriage can make life bitter. Friends and family play a vital role in resolving such domestic problems. The intent of this production, in my view, was a good idea. This play speaks to everyone; the married and the unmarried. It helps us examine our families, our actions and how best we understand the people around us. There are two main issues raised in the play that make it important and applicable. First, through the life of Heines and the unfaithfulness of her husband, the play reminds us of the importance of safeguarding marriages and building strong family ties. The suffering brought to Haines through her husband’s infidelity is traumatizing. The play further highlights the need to solve domestic or marital problems without taking rush decisions. Secondly, the play helps us re-examine the role played by our friends in our lives. In the play, Selvia knew that Heines’ husband had an extramarital affair yet she did not inform her friend about it. She instead spread the rumor among other women. This play thus allows the audience to examine whether or not to keep some of their friends. In particular, this play reminds us of the role friends play in marriages. Overall, the play challenges and provokes the audience. The intention is to make people examine their behaviors, beliefs and their general view of life. This play succeeds in provoking us into asking ourselves questions regarding our lives, and how we treat those around us. After watching the play, I believe that the play achieved its purpose. First, in a good play, characters need to portray the events as real as they possibly can. In this play, the characters portrayed

An analysis of two engineering Forms of Contract Coursework

An analysis of two engineering Forms of Contract - Coursework Example These benefits are in terms of cost b saving, improvement of quality of both services and products, and time-saving. The very first NEC contract was published in 1993. The abbreviation NEC stands for New Engineering Contract. This new type of engineering contracts was a radical shift from the traditional contracts that existed before the year 1993. Unless the previous contracts, this contract is written in plain language. The contract abandoned the frustrating nature of the previous engineering projects and concentrates on stimulating the parties involved. After the first edition of NEC contract, the second edition was published. This new edition was called the NEC Engineering and Construction Contract. This was only two years after the NEC contract was published. This new NEC contract had Adjudicators Contract, a new professional service and subcontracts together with a set of back-to-back short forms. In April 2013, this suite was enlarged and updated. The new move saw the total number of documents making it rise to 39 documents. These documents included Professional Services Short Contracts and a set of enhanced guidance documents. The professional services short contracts are the standard form used to appoint project managers by the Association of project Management. The updated NEC contract is called the NEC3. The NEC3 is recognized worldwide for its unrivaled track record. This has seen it getting endorsements from both industry and governments all around the world. Some of the major engineering projects that have been delivered by this contract within budget and on time are the venues for both the 2012 London Olympic venue and the Paralympic games venue. This projects put the NEC3 onto a whole new level. FIDIC’s standard form of contract is much older than the NEC3 contract which is quite recent. This type of contract is

Series Pass Voltage Regulator From Discrete Electronic Engineering Essay

Series Pass Voltage Regulator From Discrete Electronic Engineering Essay The objective of this project was to construct and design a 9V  ± 0.3V, 1A series pass voltage regulator from discrete electronic parts. The voltage regulator must exhibit a voltage regulation of 5% or better and should be supplied with a dc input voltage. The regulator circuit was required to include a way to disconnect the load from the regulator if the load current exceeded 1A or if the temperature of the series pass element exceeded 40 °C. It was necessary to measure each parameter of the circuit and convert it from an analog to a digital signal. This signal would provide data necessary to display the values on the Spartan III FPGA Development Board. The numerical display was not to have any zeros leading a number, unless it affected the value. Also, the display was to be cyclic, alternating at 5 second intervals. The circuit was designed, built and tested. It produced 9.03V output and 1.02A through a 9à ¢Ã¢â‚¬Å¾Ã‚ ¦ load. The cut-off protection worked as well as the variable sensing circuitry. The linkage of the analog and the digital components, however, remain incomplete. Contents LIST OF FIGURES LIST OF TABLES LIST OF ABBREVIATIONS AND SYMBOLS Symbol Description ADC Analog to Digital Converter Op-amp Operational Amplifier V Voltage/Volts I Current R Resistance A Ampere à ¢Ã¢â‚¬Å¾Ã‚ ¦ Ohm  °C Degree Celsius F Farad IC Collector Current IB Base Current VBE Base-Emitter Voltage LUT Look Up Table BCD Binary Coded Decimal MUX Multiplexer CLK Clock DPDT Double Pole Double Throw FPGA Field Programmable Gate Array Table : List of Abbreviations Contained in this Report INTRODUCTION Commercial power is usually distributed with an AC supply. An unregulated voltage such as this could cause damage to many household appliances and electronic devices. Therefore it is a safety hazard. A voltage regulator is a device that maintains a relatively constant output voltage for a varied input voltage. It functions by comparing the output voltage to a fixed reference and minimizing this difference with a negative feedback loop. The aim of this project to design a series pass voltage regulator with an output of 9  ± 0.3V and regulation of at least 5%. It should be able to disconnect the load from the regulator for temperatures exceeding 40à ¢Ã‚ Ã‚ °C and a current greater than 1A. Using A/D converters, these values (output regulator voltage and current, temperature of the series pass transistor) were converted to digital format and displayed on the Spartan III FPGA Development Board. Each value received from the analog component should be displayed with no unnecessary leading zeroes. The display had to alternate between different variables of voltage, current and temperature. The Digital Component of this project was designed in Xilinx ISE 7.1i, and the necessary tests were carried out. A User Constraints file was created, which allowed for the programming of the FPGA Board. BACKGROUND THEORY AND LITERATURE REVIEW Using an unregulated power supply is unfeasible for most tasks. This is because as the load current increases, the ripple voltage increases and the DC output voltage decreases. The voltage regulator greatly reduces ripple and produces a steady output voltage for a range of input voltages. Different types of voltage regulators have different functions. There are two main types, shunt and series voltage regulators. Shunt Voltage Regulator For a shunt voltage regulator, the regulating device is placed in parallel with the load. A resistor is placed in series with the load and the unregulated supply. The current is varied through the control element depending on the load current. This causes a voltage drop across the resistor in series, maintaining a constant load voltage. (Prof. Gift, 2012) Figure : Shunt Voltage Regulator Shunt Voltage Regulator Example: Zener Diode Regulator Figure : Zener Diode Voltage Regulator The zener diode is a semi-conductor diode designed to operate in the reverse-biased region. In forward bias, it functions as a normal diode but when in reverse bias, it breaks down for voltages exceeding the breakdown voltage, or zener voltage. For operation in this region a current Iz is required where the limits being the minimum and maximum current for the diode to operate without breaking down. (Prof. Gift, 2012) Series Voltage Regulator For a series voltage regulator, the regulating device is placed in series with the load and the unregulated supply. (Prof. Gift, 2012) The output voltage is sampled by a circuit that provides a feedback voltage to be compared to a reference voltage. If the output voltage increases, the comparator circuit provides a control signal to cause the series control element to decrease the amount of the output voltage, thereby maintaining the output voltage. If the output voltage decreases, the comparator circuit provides a control signal to cause the series control element to increase the amount of the output voltage. (Electronic Devices and Circuit Theory 7th Ed.) Figure : Series Voltage Regulator There are different circuit topologies for the series voltage regulator. These will be examined next. Simple Series Transistor Regulator To improve the current capacity of the zener diode regulator, a transistor is used in the emitter follower configuration. This acts as the series control element. The collector is supplied by the regulated voltage. The transistor reduces the load current capacity of the zener by a factor of the transistor current gain. The zener voltage is therefore produced at the emitter. The equation IC = ÃŽÂ ²IB is used to link the collector current and the base current. Due to high current gain, even very large changes in IC result in only small changes in IB. This means IZ is mostly stable. The input voltage must be greater than the diode voltage to ensued proper transistor bias. (Prof. Gift, 2012) Figure : Simple Series Transistor Voltage Regulator IZ current through the zener diode IC collector current IB base current Discrete Voltage Regulator A transistor Tr2 is connected as the series pass transistor and another one Tr1 acts as the error amplifier. In the single transistor regulator output ripple voltage is low, but the output voltage still varies. This is due to the VBE/IC characteristic of the transistor. Feedback is used to correct the output. This amplifier compares the sampled voltage with a reference voltage in order to generate a signal proportional to the difference. This is used to drive the series pass element, which then varies the output voltage such that the error is reduced and the output voltage regulated. Figure : Discrete Transistor Voltage Regulator The voltage across the series element is (Vin Vout). The input voltage to the error amplifier is ÃŽÂ ²Vout Vref, where . The output voltage across the series element is an amplified version of the input voltage, . If Vref is constant, . This is the stability factor. This means that the ripple voltage is reduced by a factor of . The higher the loop gain, AÃŽÂ ², the better the regulator performance. A is gain of error amplifier. The resistor R can be connected to the regulated side of the circuit to improve the design and decrease ripple voltage. Also, a capacitor may be placed in parallel to the Zener diode. Another capacitor can be placed across the output removing output noise and input impedance at high frequencies. A Darlington Pair may be used as the series element. This has two transistors in a single package. The Darlington Pair increases the current gain of the series element, making it able to supply a larger load current if required. (Prof. Gift, 2012) Operational Amplifier Series Voltage Regulator In order to improve the regulator performance, the loop gain A is increased. A simple method of doing this is to replace the transistor error amplifier with an operational amplifier as shown in figure 6. The operational amplifier compares the reference voltage of the zener with the feedback voltage sampled by resistors R1 and R2. The Darlington Pair design is used here and R3 connected to the regulated supply to reduce the ripple voltage. The operational amplifier (op amp) must be supplied by the unregulated input voltage. (Prof. Gift, 2012) Figure : Operational Amplifier Series Voltage Regulator STANDARDS Certain standards were considered in the undertaking of this project. These are: ISO 9001:1994 Quality Systems Model for Quality Assurance in Design, Development, Production, Installation and Servicing (http://www.ttbs.org.tt/) TTS 620 2008 Occupational Safety and Health Risk Assessment Requirements(http://www.ttbs.org.tt/) BS QC 790304:1994 Specification for harmonized system of quality assessment for electronic components. (http://www.standardsuk.com) RISK ASSESSMENT Possible Hazards: 15V supply voltage. Risk of electrical shock, burns and death. Solder fumes present. Dangerous if inhaled. The heat generated by the power resistor could cause burns. The tip of the soldering gets very hot and could cause severe burns or start a fire. Clipping wires and leads may cause them to be projected into eyes and face. Steps Taken to Avoid Risk: Ensured that student was properly grounded. Proper clothing and footwear were worn. No long hanging jewellery or hair. Before energising a circuit, it was checked by a technician. Tested conductors before handling them. Exhaust fan present in lab. Regularly stepped outside for fresh air. Clipped wires away from face of anyone present. DESIGN APPROACH AND METHODOLOGY Project Requirements: Design and build a 9V  ± 0.3V, 1A Series Pass Voltage Regulator using discrete electronic components. Regulator must have a voltage regulation or 5% or better and must be fed by a dc input voltage from a laboratory power supply. In addition, the regulator must incorporate temperature and over current sensing circuits which would disconnect the load from the regulator, for temperatures and currents exceeding 40 degrees centigrade and 1 A respectively. The output regulator voltage and current, together with the temperature of the series pass transistor must be converted to digital format using A/D converters and displayed on the Spartan 111 FPGA Development Board when selected. The following specifications must be met for the display of the variables: 1. The units of all variables are to be displayed along with the respective reading. 2. The voltage is to be displayed to 1 decimal point. 3. The current is to be displayed to 2 decimal points. 4. The temperature is to be displayed as a whole number. 5. The display of the readings for voltage, current and temperature are to automatically appear in a cyclic manner, with each reading being displayed for 5 seconds. 6. All leading zeros are to be suppressed. (ECNG 2004 Design Project Description) This design had both an analog and a digital component. ANALOG COMPONENT This component involved the design and construction of the Series Pass Voltage Regulator and the sensing circuitry to detect current, voltage and temperature. These sensors were constructed to relay the values necessary for the digital component. Analog to Digital Converters were designed to convert the analog output from the current, voltage and temperature sensing circuits to digital format so as to be to be read by the Spartan FPGA Board. Design of the Operational Amplifier Series Voltage Regulator Figure : Circuit Diagram of the Operational Amplifier Series Voltage Regulator The regulator was powered by a DC input voltage from a laboratory power supply. The voltage used in the design process for the purpose of calculation was 15 volts. Choosing the Zener Voltage and Zener Current The Zener Voltage, Vz was supplied by the Zener Diode, D1 as shown in Figure 7 above. The Zener Voltage was used as a reference voltage by the Operational Amplifier. The op amp is functioning as a differential amplifier in this situation. The difference between the inputs at the inverting and non-inverting terminals is amplified. Gain, The output voltage, VZ zener voltage Vz should be high enough so that gain would not decrease to achieve the required output. If Vz was too high, i.e. the output voltage, no current would flow through D1. An appropriate value between 0V and 9V was chosen, VZ = 4.8V. The IN4732 Zener Diode was chosen and the specification sheet for this model was obtained. The specified test current was 53mA, and the chosen value was 40mA. This was chosen to ensure proper bias. Calculating Resistor R3 The resistor R3 was in series with the Zener Diode. Therefore, the current through them is the same. A 100 à ¢Ã¢â‚¬Å¾Ã‚ ¦ resistor was chosen as it was the closest one in value available in stores. R3 = 100à ¢Ã¢â‚¬Å¾Ã‚ ¦ Calculating Resistors R1 and R2 Resistors R1 and R2 formed a potential divider providing the inverting input of the op amp. This sampled the output and sent it to the error amplifier. If the value of the output changed from the designed, the voltage drop across the resistors would change and the op amp input voltage would change, producing an error voltage at the output of the op amp. This error voltage will either turn on more or turn off more Transistor Tr1 and effectively Tr2 as well. The output voltage, Vo is related to the Zener Voltage by the equation below. Substituting Vo = 9V and Vz = 4.8V, Therefore, If R2 chosen to be 10kà ¢Ã¢â‚¬Å¾Ã‚ ¦, then Therefore, R1 = 8.8kà ¢Ã¢â‚¬Å¾Ã‚ ¦ and R2 = 10kà ¢Ã¢â‚¬Å¾Ã‚ ¦. Choosing an Operational Amplifier The LF351 op-amp was chosen for this design. It only needed to function as a differential amplifier. Choosing the Series Pass Transistor The required output current was 1 Ampere. Therefore the maximum collector current of the series pass transistor had to be greater than 1 A. high power transistor was needed, but the current gain of power amplifiers is low (approximately 40). The base current and collector current for a transistor are related by the following expression. Substituting Current gain, hfe = 40 and Ic = 1 A, The LF351 op amp could not supply this base current. A Darlington Pair arrangement was used instead. Darlington Pairs have high current gain. The high power transistor chosen was TIP31C, packaged in a TO-220 Case. The current gain, hfe1 of this transistor was specified to be between 10 and 50, so a value of 30 was used. An NPN medium power transistor, BFY51 in a TO-39 metal package, was chosen for Tr2 in Figure 6. The current gain, hfe2 was found to be 123. Hence, total current gain of the Darlington Pair: hfe1 ÃÆ'- hfe2, i.e. 30 ÃÆ'- 123 = 3690. Substituting Current gain, hfetotal = 3690 and Ic = 1 A, Design of the Voltage Sensing Circuit The purpose of the Voltage Sensing Circuit was to determine the output voltage of the regulator and relay this voltage to the Analog to Digital Converter input. The Analog to Digital Converter (ADC) chip (ADC08040 IC) had a reference voltage of 4.5V. The maximum voltage possible was 9.5V. Hence if the voltage output was 9.5V, the ADC08040 input voltage should be 4.5V. VO had to be stepped down by a potential divider before it could be sent to the ADC08040. It was stepped down by a factor of . Let R1 = 1kà ¢Ã¢â‚¬Å¾Ã‚ ¦, then R2 = 1kà ¢Ã¢â‚¬Å¾Ã‚ ¦ This voltage was sent to a Unity Gain Voltage Follower (Figure 8) and was input to the ADC circuit. (Prof. Gift, 2012) Voltage Sensor.bmp Figure : Voltage Sensing Circuit Design of the Current Protection Circuit The purpose of this was to disconnect the load from the regulator when the current flowing through the load surpassed 1A. The protection circuit monitored the load current and sent a signal to a device to disconnect the load, when the current rose to over 1A. A 1à ¢Ã¢â‚¬Å¾Ã‚ ¦ shunt was used in series with the 9à ¢Ã¢â‚¬Å¾Ã‚ ¦ load resistor. The shunt voltage was used to determine cut-off. An instrumentation amplifier was chosen (INA114AP) to compare the temperature sensor voltage and a potential divider voltage. The shunt voltage was amplified to increase chances of accurate determination of when to disconnect the load. A potential divider was constructed to deliver a4V, and the shunt voltage was also amplified to 4V. Potential Divider: Which gives: Let R1 = 20kà ¢Ã¢â‚¬Å¾Ã‚ ¦ The voltage from the shunt was amplified to 4V as well, and this was done by an op-amp and two resistors set up in the non-inverting amplification configuration shown below. The reference used to be amplified was 0.9V from the shunt, as this was the value which, if exceeded, cut-off and disconnection of the load was supposed to occur. For an non inverting amplifier, Vo = 4V, Vi = 0.4V, And Let R1 = 2.4kà ¢Ã¢â‚¬Å¾Ã‚ ¦, R2 = 8.2kà ¢Ã¢â‚¬Å¾Ã‚ ¦ .Temperature Amp Input to INA.bmp Figure : Circuit for Comparison and Determination of Cut-off When both inputs have the same voltage across them, the instrumentation amplifier would have an output of zero. The transistor in Figure 10 would be turned off and the base would be at 0V. The transistor used was a 2N3904 (Ic = 200mA). If the output is non-zero, the base would be driven by a voltage and the transistor will be ON. When the output is zero (same inputs) the transistor would be OFF and the relay coil would be grounded through the transistor. Current would flow through the coil, producing a magnetic field, and the relay would latch. When the instrumentation amp inputs are different, the output would saturate at +Vcc, i.e. 9V. The coil would an equal voltage at either end and so would have no voltage drop across it, meaning no current flowing through it. The relay is effectively OFF. There is a Normally Open (N.O.) Switch between pins 2 3, and 7 5 of the relay as well as Normally Closed (N.C.) Switches across pins 2 3 and 7 6. The N.O. switches close and the N.C. switches open when the relay latches. The load was connected across the N.C. pins. When the instrumentation amp has the same inputs, (zero output), and there is a voltage drop across the coil, current flows and the relay latches, disconnecting the load from the circuit. The relay had a rated voltage of 6V and the coil had a measured resistance of 70.5à ¢Ã¢â‚¬Å¾Ã‚ ¦. The relays, however, were actually found to latch at a voltage of 3.2V. Therefore for calculation purposes 3.5V is used = 49.6mA was needed to latch the relay. A potential divider was used to provide the required voltage for the relay. For a resistor R3, This caused a voltage drop across the coil, larger enough to activate the coil when necessary. The voltage across resistor R3 is given by, For Ic = 49.6mA, The Base Current of the transistor is given by For Ic = 49.6mA, and hfe = 100, To bias the base of the transistor for the 9V output of the op-amp, A 16kà ¢Ã¢â‚¬Å¾Ã‚ ¦ resistor was used. This would change VBE of the transistor. The new VBE was well within the operating range required for the resistor. Temperature Cutoff.bmp Figure : Current Protection Circuit Design of the Current Sensing Circuit The Current Sensing Circuit determined the voltage regulator output load. This value of current would be received by the ADC input. The ADC chip (ADC08040 IC ) was 4.5V. The Current LUT could convert a maximum of 1.29A. This means when the regulator reaches 1.29A, the ADC will be at 4.5V. A 1à ¢Ã¢â‚¬Å¾Ã‚ ¦ shunt resistor was placed in series with the load. The 9V regulated output would now be applied to a combined load of 10à ¢Ã¢â‚¬Å¾Ã‚ ¦. Voltage drop across the shunt: Therefore: The output voltage across the shunt is 0.9V. This will correspond with the maximum voltage which will give all 1s at the ADC output. Thus the voltage must be stepped up using a non-inverting op-amp. The voltage of 0.9V was stepped up to 4.5V. This means the gain is = 5 Let R1 = 2k à ¢Ã¢â‚¬Å¾Ã‚ ¦. Therefore, R2 = 8kà ¢Ã¢â‚¬Å¾Ã‚ ¦ The potential divider voltage was passed through the amplifier and then input into the ADC. Current Sensing Circuit.bmp Figure : Current Sensing Circuit Design of the Temperature Protection Circuit This disconnects the load from the regulator when the temperature of the Power Transistor (TIP31C) reached 40 °C. The Power Transistor temperature was monitored and at 40 °C, a signal would be sent from the circuit to a device, disconnecting the load. The LM35DZ was chosen. Its sensitivity was 10mV/ °C. At 40 °C, the temperature sensor output would be 0.4V. An instrumentation amplifier (INA114AP) was chosen to compare the temperature sensor voltage and the potential divider voltage. For a more accurate determination of the load, the temperature sensor output voltage was amplified. The potential divider delivered a voltage of 4V, and the sensor output voltage was also amplified to 4V. Therefore: Let R1 = 20kà ¢Ã¢â‚¬Å¾Ã‚ ¦ An op amp and two resistors were used to build a non-inverting amplifier in order to set the temperature sensor voltage to 4V. The reference voltage was 0.4V, since it is at this point cut-off should take place. For a non-inverting amplifier: , , Let R1=1kà ¢Ã¢â‚¬Å¾Ã‚ ¦ and R2=9kà ¢Ã¢â‚¬Å¾Ã‚ ¦, Temperature Amp Input to INA.bmp Figure : Amplifier Circuit for Comparison and Determination of Cut-off . When both input voltages are the same, the amplifier output would be 0V, turning off the transistor. (No VBE present). A 2N3904 transistor was used (Ic = 200mA), so the current would be large enough to latch the relay. If the amplifier output is not 0V, there would be a voltage drop across the base and the transistor would be ON. When the amplifier output is 0V, the transistor would be OFF, grounding the relay, causing current flow in the coil, latching the relay. When the amplifier inputs are at different levels, the output saturates at +Vcc = 9V. Equal voltages exist at both ends of the coil, so no current flows hence the relay is OFF. A Normally Open (N.O.) Switch exists across pins 2 3, and 7 5 of the relay. Normally Closed (N.C.) Switches exist across pins 2 3 and 7 6. The N.O. switches close and the N.C. switches open upon latching. Consider this load connected across the N.C pins and the amplifier has equal inputs. The amplifier output is 0V, causing a voltage drop across the relay coil, causing current flow and latching of the relay. It follows then that the load is disconnected from the circuit. For a resistor R3, R3 was used to activate the coil by creating a voltage drop across it. For Ic = 49.6mA, For biasing, A 16kà ¢Ã¢â‚¬Å¾Ã‚ ¦ resistor was used instead. Temperature Cutoff.bmp Figure : Temperature Protection Circuit This circuit was designed to relay the temperature of the power (TIP31C) to the ADC input. The ADC chip (ADC08040 IC ) reference voltage was 4.5V. The Temperature LUT could convert up to 129à ¢Ã‚ Ã‚ °C. At this temperature, the ADC should be 4.5V. A Temperature Sensor (LM35DZ) in a TO-92 package used to determine the temperature. This had a sensitivity of 10mV/ °C. At 129 °C, VO = 1.29V. Sensor output voltage was stepped up using a non-inverting op amp by a factor of , Let R1 = 1k à ¢Ã¢â‚¬Å¾Ã‚ ¦. R2 = 2.49kà ¢Ã¢â‚¬Å¾Ã‚ ¦ à ¢Ã¢â‚¬ °Ã‹â€  2.5kà ¢Ã¢â‚¬Å¾Ã‚ ¦ The sensor voltage was amplified and input into the ADC. Temperature Sensing Circuit.bmp Figure : Temperature Sensing Circuit A copper strip board was used to build the voltage regulator circuit since the solderless breadboard could only take up to 0.5A. Inputs: Voltage Supply of 15V Outputs: Voltage Sensing Output OV Ground Regulated 9V Output Temperature Sensing Voltage A voltage follower was used to buffer the output. The circuit was constructed as seen in figure 15: Figure : Complete Sensing and Cut-off Circuit DESIGN OF THE ANALOG TO DIGITAL CONVERSION CIRCUIT An 8 bit representation was used with reference to the 4.5V signal. The analog signal was converted to a digital signal from the 3 sensing circuits using the schematic shown below. Analog to digital conversion was done using the. A resistor pack was used to provide over current protection. This circuit was built and tested for each of the three sensing circuits. A combination of LEDs was used for the input of the analog voltage. AD Converter Circuit.bmp Figure : Schematic for ADC control configuration Op amps were used to buffer the inputs. The outputs were mapped onto the respective pins of the 40-pin IDE cable used to interface with the Spartan III Board. Figure : 40 Pin Expansion Connector (Spartan III Toolkit Datasheet) Data was transmitted using these pins to the ADC. DIGITAL COMPONENT The FPGA board was programmed so as to use the Seven Segment Display. Xilinx ISE 7.1i was used to design and construct the display for all the variables. Design of the Basic Display Unit Multiplexers, Frequency Dividers, a Look up Table Device and a Binary Coded Decimal to 7-Segment Converter were used to create the Display Unit. The 16-bit 31 Multiplexer Multiplexers may have more than one input but usually have one output. A combination of numbers is assigned to each input pin. Using these combinations, the respective input data is sent to the output pin. Therefore the bits that are chosen which input data set to display. In this design, two multiplexers were used, a 4-bit 41 and a 16-bit 31 multiplexer. 31 means 3 data inputs, 16- bit means each input is of 16 bit capacity. 16bit3to1muxschem.bmp Figure : Schematic Diagram of a 16-bit 3 to 1-line Multiplexer The 4-bit 41 Multiplexer The 4-bit 41 multiplexer can handle up to four combinations of inputs. To select which input is displayed, two bits are necessary. The output was a bus of width 4 bits. It split the 16 bit output into four sets of 4 bits. The 4-bit 41 multiplexer is shown in figure 19. 4bit4to1mux.bmp Figure : Schematic Diagram of a 4-bit 4 to 1-line Multiplexer Binary Coded Decimal (BCD) to 7-Segment Display Unit The BCD unit accepts four bits of data, e.g. D3D2D1D0, and determines which segments of the 7-segment display to turn on and off so as to represent the value of the input data. Figure 20 shows a 7-segment display. This type of display is common in electronic equipment e.g. calculators, microwaves, digital clocks. The Minimum Expressions for the BCD are: Seg_a = D3D2D1D0 + D2D1D0 + D3D2 + D3D1 Seg_b = D2D1D0 + D2D1D0 + D3D2 + D3D1 Seg_c = D2D1D0 + D3D2 + D3D1 Seg_d = D2D1D0 + D2D1D0 + D2D1D0 + D3D1 + D3D2 Seg_e = D0 + D2D1 + D3D1 Seg_f = D3D2 + D2D1 + D1D0 + D3D2D0 Seg_g = D3D2 + D3D1 + D2D1D0 + D3D2D1 For each expression, logic gate circuits were created. Each segment was then used to build the final BCD to 7-Segment Converter. The combinations of segments that would form the values were organised. The Look-Up-Table (LUT) This was used to determine which display unit anodes were to be turned on and off. There were four individual 7-segment displays. Each one had its own anode and as such could be controlled by choosing the anode of the respective display. lut.bmp Figure : Schematic Diagram of a Look-Up-Table (LUT) Modulo 4 Counter The Modulo 4 counter was used to perform automatic cycling of the anodes to be displayed. Only one anode was on at a time for each different combination. Moduloo4counter.bmp Figure : Schematic Diagram of a Modulo 4 Counter For multiplexed displays, the entire display is not lit up as the same time. The characters are made up of segments which, under certain conditions, become active. Each character is displayed one at a time. Switching of characters takes place so fast it appears that all the displays are on at the same time. The speed of switching is called the frequency divider (in this case 1kHz). This activates the modulo 4 counter which causes the LUT to choose one of four inputs to be chosen from the 4-bit 4 to 1 multiplexer to send to the 7 segment display. The Combined Display Unit Data Unit.bmp Figure :Schematic Diagram of the Display Unit Upgrade of the Display Unit to display the Decimal Point The LUT controls the switching of the anodes on the four 7 segment displays. Each 7 Segment Display has a decimal point that can be turned on or off if necessary. This was necessary in this project when displaying voltage and current. For a voltage, the decimal point is on the 3rd anode, a2. 0 9. 0 V For a current, the decimal point is on the 4th anode, a3. 0. 9 9 A This means that the point will only be on when S0 and S1 select to display voltage or current, and when the third or fourth anodes are on respectively. The Essential Prime Implicants were chosen from a truth table and the minimized expression was produced as follows: The Logic Gate circuit was constructed as shown below and implemented in Xilinx ISE 7.1i. A Macro was then created and connected appropriately in the Updated Display Unit Schematic. Decimal Point Upgrade.bmp Figure : Logic Gate Circuit for Decimal Point Upgrade Upgrade of the Display Unit to display the Units for each Variable The Display Unit was upgraded a second time in order to allow the units of each parameter to show Parameter Unit Symbol for Unit Voltage Volts V Current Amperes A Temperature Degrees Celsius à ¢Ã‚ Ã‚ °C Table : Parameters to be Displayed and their Respective Units The BCD Converter had to be updated to ensure when certain select bits were chosen, the segments would align to form the unit symbol on the first anode. Since there are four select inputs, D3D2D1D0 , there are 16 possible combinations of these bits forming different outputs. 0000 to 1001 in binary form represents 0 to 9 in decimal form. This means that there are combinations 1010 to 1111 to choose from to display a unit. 1101 was chosen for voltage, 1110 for current and 1111 for temperature. Figure : Common

Just another Crazy Woman on the edge of Time :: Woman on the edge of Time Essays

Just another Crazy Woman on the edge of Time  Ã‚  Ã‚     Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚   In Woman on the edge of Time, by Marge Piercy, a middle aged Chicana woman from New York finds out that she a can communicate with the future. She finds herself able to be in more than one time. She is, as far as we know, the first to be able to do this. There were others, but they all closed themselves off, thinking themselves insane when the â€Å"voices from the future† began to speak. Connie’s connection was probably simpler because of the similarities between the world in which she lived now (in the mental hospital) and the world of the future.   Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚   The societal systems of the two worlds are very similar. If you exclude the doctors of the mental hospital, all are equal. Each ward can be a different village, with different cultures and governmental systems. Connie moves from ward to ward in her time as she moves from town to town in Luciente’s time. In each ward (as in each village) she learns something new. In the first, she gives up and accepts. In the second she survives and struggles to keep her sanity. In the third she learns the necessity of the fight. Each ward has something new to experience. In each village, she learns a new idea/concept/truth about the way her world (outside the hospital) really is instead of how she sees it.   Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚   In the mental ward, there is no economic system. Sure, money exists, but it doesn’t come from inside the ward. It is an alien thing; a luxury as are all of the others. The wards that Connie lives in are all filled with their own luxuries. In one, you find card tables and cards, puzzles and chairs. In another ward there are separate rooms and bathrooms with doors, all of which are shared by the general public (the patients). There is no special treatment. Who ever wants to use the cards or the puzzles can. Almost like the dresses/costumes that are rented from the library in Mattapoisett time. There, we use bicycles as we find them. â€Å"Any bike not in use, I can use.† (p 364). If the cards aren’t being used buy someone else, you have every right to use them.   Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚   People are just as free. Relationships in the future are a bit more open than those that Connie has had. Just another Crazy Woman on the edge of Time :: Woman on the edge of Time Essays Just another Crazy Woman on the edge of Time  Ã‚  Ã‚     Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚   In Woman on the edge of Time, by Marge Piercy, a middle aged Chicana woman from New York finds out that she a can communicate with the future. She finds herself able to be in more than one time. She is, as far as we know, the first to be able to do this. There were others, but they all closed themselves off, thinking themselves insane when the â€Å"voices from the future† began to speak. Connie’s connection was probably simpler because of the similarities between the world in which she lived now (in the mental hospital) and the world of the future.   Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚   The societal systems of the two worlds are very similar. If you exclude the doctors of the mental hospital, all are equal. Each ward can be a different village, with different cultures and governmental systems. Connie moves from ward to ward in her time as she moves from town to town in Luciente’s time. In each ward (as in each village) she learns something new. In the first, she gives up and accepts. In the second she survives and struggles to keep her sanity. In the third she learns the necessity of the fight. Each ward has something new to experience. In each village, she learns a new idea/concept/truth about the way her world (outside the hospital) really is instead of how she sees it.   Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚   In the mental ward, there is no economic system. Sure, money exists, but it doesn’t come from inside the ward. It is an alien thing; a luxury as are all of the others. The wards that Connie lives in are all filled with their own luxuries. In one, you find card tables and cards, puzzles and chairs. In another ward there are separate rooms and bathrooms with doors, all of which are shared by the general public (the patients). There is no special treatment. Who ever wants to use the cards or the puzzles can. Almost like the dresses/costumes that are rented from the library in Mattapoisett time. There, we use bicycles as we find them. â€Å"Any bike not in use, I can use.† (p 364). If the cards aren’t being used buy someone else, you have every right to use them.   Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚   People are just as free. Relationships in the future are a bit more open than those that Connie has had.

The Issue of Territorial Exspansion Sparked Considerable Debate in the Period 1800-1855.

Gregory Ortega Big bang Scientist around the world studies the stars and planets to learn more about the past or to learn how that and our planets are alike. But then there are other scientist who got even deeper and learn what created the planets and stars these scientist are called astronomers and we have learned so much from the science and research they do every day. One major theory from the scientist is that the universe was created by the mixture or gases and matter. And the gases and matter collided into each other until a huge explosion occurred that form suns and giant rocks that later formed into stars and planets. According to the big bang theory a great explosion occurred over 13. 5 billion years ago because of the mixture of dark matter and gases. The fusion occurred when the universe was a small as a period at the end of a sentence. This spark created the planets, stars, and galaxies we know and learn about now. We also know this because of random glows from all around the universe left from the big bang these glows are known as cosmic background information. The planets were first asteroid like blocks that collided with one another to create planets this happened over many years and formed planets all around the universe. The Doppler effect is a part in showing us more about the universe and waves it produces the Doppler effect is A change in the observed frequency of a wave, as of sound or light, occurring when the source and observer are in motion relative to each other, with the frequency increasing when the source and observer approach each other and decreasing when they move apart. The motion of the source causes a real shift in frequency of the wave, while the motion of the observer produces only an apparent shift in frequency. Also a another thing that’s shows us waves from space is when u turn on a TVs and static would show or when u used a radio and static would come up between the stations the waves that shows are called electromagnetic spectrum. When u looks up into space you see many doted stars that cover the sky these dots are stars that are much father from our usual sun. he father the star is the redder it will be the closer the bluer these color differences are called the red and blue shift. Our solar system holds all 7 planets and sun including our earth our solar system is very special because it keeps our earth at a perfect temperature and the force form our sun isn’t to major to the point that we get burnt alive just by rotating around it, the sun does a major part because it uses its gravity to keep us in place rotation around it and the sunlight produces energy we use for appliances. all these things are in our galaxy.

Course Syllabi- History of Graphic Design Essay

Course Description History of Graphic Design is a critical contextual research and survey study of the intents, influences, practices, and artifacts of graphic design. The course will be structured on readings, research, and visual presentations on subjects of designer activities throughout history with an emphasis on the broader historical context of the planning, production, form, distribution, reception and cultural integration of graphic design Student Handbook The Student Handbook is now available digitally rather than in hard copy. It can be found on the PNCA website (under Student Life) and on Homeroom (Home page, under PNCA Essentials). Disability Support PNCA is in compliance with federal law requiring colleges to provide reasonable accommodations for students with documented physical and/or learning disabilities. If you have a disability that might affect your performance in this class, please make it known to the instructor. Learning Outcomes At the conclusion of this course, the student should be able to : - ­Ã¢â‚¬  Demonstrate and articulate in discussions, writings, and visual presentations an understanding of the historical context of the creation of a work of graphic design (i.e. – time, place, culture, intents) - ­Ã¢â‚¬  Synthesize readings and lectures and be able to formulate and post discussion points and prepare visual examples for peer review and feedback (as comments) using online tools - ­Ã¢â‚¬  Utilize, and bibliographically document, a range of resources used for the study of the history of graphic design (books, journals, periodicals, online, interviews) - ­Ã¢â‚¬  Creative Practice Identify the roles, activities, and trades of communication design professionals throughout history and distinguish specific fields related to and integrated with the profession of graphic design - ­Ã¢â‚¬  Learning Outcomes are linked to PNCA’s Core Values which are: Identify and articulate the influence of fine art (theories, trends, aesthetics, visual styles) on the work of graphic designers Integrated Knowledge, Critical Thinking, & Cultural Inquiry Social and Ethical Responsibility Course Content initiate, and participate in, discussion on the planning, process, production and distribution of works of graphic design - ­Ã¢â‚¬  Effective Communication - ­Ã¢â‚¬  formulate a connection of the cultural influences on design from history with practices of contemporary graphic designers through examples, writings, and discussions Assignments for this Class: - ­Ã¢â‚¬  - ­Ã¢â‚¬  - ­Ã¢â‚¬  - ­Ã¢â‚¬  Required Readings and discussion with evidence of comprehension Weekly Subject Research and On-line Posting to Homeroom Weekly In-Class presentations Final Research Paper Topics for weekly research will include: Design during Cultural Upheavals / World Conflicts Design for Social Causes / Design for Social Good Design for Commerce, Consumption, Commercialism Information Design / Dissemination and Distribution of Information Technological Changes and its Influence on Graphic Design Design as Author, Designer as Artist, Whole Designer The Concept of Brand and the Development of Brand Identity Low Design / Bad Design Major Benchmarks in Typography Reactionary Design / Culture Jamming Expectations/Policies for this course: Students are required to read and to be ready to articulate a response to all readings assigned in class. Each week there will be an assigned subject research topic that will require independent sourcing, image documentation, writing, and on-line posting on the ‘Homeroom’ site established for the course. Each student will make a 5-10 minute presentation of each assignment postings during classtime with an expectation of the use of prepared supported notes for verbal elaboration on the material presented. In-class and on-line participation in the form of response and discussion and will be expected and recorded. A final research project on the relatedness of the topics of historical practice presented to the practices of a contemporary designer or design firm/group will be in the form of a research paper. (8-10 pages minimum) Attendance You will be allowed two absences without additional penalty – although you are responsible for any work that is missed. The third absence will result in the lowering of an entire letter grade from the computed final grade. A fourth absence will result in a final failing grade of F. Missing 30 minutes of a class period (during any part of the scheduled classtime) counts as an absence. Frequent tardiness (less than 15 minutes) will accumulate to absences (3 tardies =1 absence) Number of hours students are expected to work outside of class: This class meets for three hours per week, and six hours of work outside of class are expected. (3 credits) Grading Criteria †¢ Weekly Research Assignments timely completion / in-class presentation preparedness and comprehensiveness †¢ In-Class participation/contributions †¢ On-Line participation/contributions †¢ Final Research Paper Materials / Supplies Required: †¢ Access to, or ownership of, equipment to scan/photograph (digitize), upload and review visual and text information on a regular daily basis. (Computer and Camera/Scanner) †¢ Money for photocopying (approx. $20 projected) †¢ Flash Drive (2-4gb) Recommended: History of Graphic Design text purchases (Personal library) Bibliography The books listed here are predominantly larger volumes dedicated to a broad overview and history of graphic design. (More may be added during the semester) Many less comprehensive but key texts are available in the library as well as journals and periodicals that are specific to designers, styles, and various other edited groupings – these should be sought out and reviewed andutilized especially for more indepth study on a research subject. Major Texts of the History of Graphic Design Those mark with asterisk* are on reserve shelf at front desk of PNCA library and are available on 3 hr. check out (note: many of these text have duplicates or earlier editions and are available for longer check out periods if needed) Title: Meggs, History of Graphic Design, 4th Edition* Author(s): Philip Meggs, Alston Purvis Publisher: Wiley ISBN: 978047169902 Library Call#: Z 246 .M43 1983 Title: Graphic Design, a Concise History* Author: Richard Hollis Publisher: Thames & Hudson world of art ISBN 0500203474 Library Call#: NC 998 .H65 1994 Title: Graphic Design: a New History* (1st and 2nd Editions) Author: Stephen Eskilson Publisher: Yale University Press ISBN: 0300120117 Library Call#: NC 998 .E85 2007 (1st Edition in Library*) Students are invited to contribute to the additions to this bibliography through their weekly research and presentation. All sources should be cited using MLA citation methods. Title: Graphic Design History, A Critical Guide* Author(s): Johanna Drucker, Emily McVarish Publisher: Pearson/Prentice Hall ISBN: 0132410753 Library Call#: NC 998 .D78 2009 Title: Graphic Design in America* Author(s): Mildred Friedman, Joseph Giovannini, Steven Heller Publisher: Walker Art Center ISBN: 0810910365 Library Call#: NC 998.5 .A1 G65 Title: Design, Writing, Research* Author(s): Ellen Lupton, Abbot Miller Publisher: Kiosk ISBN: 1568980477 Library Call#: Z 246 .L86 1996 Title: Communication Design, Principles, Methods, and Practice Author: Jorge Frascara Publisher: Allworth Press ISBN: 1581153651 Title: A Century of Graphic Design Author: Jeremy Aynsley Publisher: Barron’s Educational Series ISBN: 0764153242 Library Call#: NC 998.4 .A96 2001 Other Readings: Journal: Visible Language 28.3, New Perspectives, Critical Histories of Graphic Design, Pt. 1 Critiques Editor and Publisher: Sharon Poggenpohl Digital reference (Links) sites should be added to online postings On-Line History of Graphic Design Reference www.designhistory.org Weekly Course Schedule Week 1 6 Sept Week 2 13 Sept Friday, 13 September is the last day to add or drop a class. All information (dates, times and assignments) in this schedule is subject to change at any point during the semester. Updates will be announced and posted. Welcome / Introductions Class Expectations / Syllabus Overview / Course Structure / Assignments Using Homeroom / Communication Expectations Course Resources Reading Assigned (Posted on Homeroom) Critical Histories of Graphic Design Discussion of Readings on the approaches to History of Graphic Design development Lecture: Brief History of Graphic Design, Pt.1 Read on Homeroom these posted excerpts for this class: Graphic Design History, a critical guide, by Drucker and McVarish, Communication Design, Principles, Methods, and Practice, by Frascara, Graphic Design, a Concise History, by Hollis, Megg’s History of Graphic Design, by Meggs and Purvis, Visible Language 28.3 New Perspectives: Critical Histories of Graphic Design, article by Blauvelt Also read (for this classes visual lecture): â€Å"Prehistoric Prelude to Graphic Design† from Graphic Design History, a Critical Guide, by Drucker and McVarish Week 3 20 Sept Lecture: Brief History of Graphic Design, Pt.2 Read on Homeroom these posted excerpts for this class: â€Å"Early Writing: Mark Making, Notations Systems, and Scripts† from Graphic Design History, a Critical Guide, by Drucker and McVarish Lecture: Conventions and Norms Overview of Weekly Research Project Topics, Objectives, Goals, Expectations, Methods Introduction of Topic 1: Design during Cultural Upheavals / World Conflict Week 4 27 Sept Student Research Presentations of Topic 1: Design during Cultural Upheavals / World Conflict Questions and Discussion Introduction of Topic 2: Design for Social Causes / Design for Social Good Week 5 4 Oct Student Research Presentations of Topic 2: Design for Social Causes / Design for Social Good Questions and Discussion Introduction of Topic 3: Design for Commerce, Consumption, Commercialism Week 6 11 Oct Student Presentations of Topic 3: Design for Commerce, Consumption, Commercialism Questions and Discussion Introduction of Topic 4: Information Design / Dissemination and Distribution of Information Week 7 18 Oct Student Presentations of Topic 4: Information Design / Dissemination and Distribution of Information Questions and Discussion Introduction of Topic 5: Technological Changes and its Influence on Graphic Design Week 8 25 Oct Student Presentations of Topic 5: Technological Changes and its Influence on Graphic Design Questions and Discussion Introduction of Topic 6: Design as Author, Designer as Artist, Whole Designer Friday, 25 October is the last day to withdraw from a class. Week 9 1 Nov Student Presentations of Topic 6: Design as Author, Designer as Artist, Whole Designer Questions and Discussion Introduction of Topic 7: The Concept of Brand and the Development of Brand Identity Week 10 8 Nov Student Presentations of Topic 7: The Concept of Brand and the Development of Brand Identity Questions and Discussion Introduction of Topic 8: Low Design / Bad Design Week 11 15 Nov Student Presentations of Topic 8: Low Design / Bad Design Questions and Discussion Introduction of Topic 9: Major Benchmarks in Typography Week 12 22 Nov Student Presentations of Topic 9: Low Design / Bad Design Monday, 18 November SP14 registration begins Questions and Discussion Introduction of Topic 10: Reactionary Design / Culture Jamming Week 13 29 Nov Thanksgiving Holiday. No class. Week 14 6 Dec Student Presentations of Topic 10: Reactionary Design / Culture Jamming Questions and Discussion Final Paper – Topic Determination Week 15 13 Dec Final Paper Draft Due – Individual Meetings Week 16 20 Dec Final Class – Course Wrap-up / Overview Friday, 20 December Last day of classes. Please note: The rest of the template is uniform for all PNCA classes, it includes: PNCA grading policy, statement on plagiarism, library & ACE. This section should be included in any electronic versions of the syllabus, but doesn’t need to be distributed to students in paper form. ACE The Academic Center for Excellence (ACE) @PNCA is a peer driven support network for students at all levels. ACE provides in person and online assistance with the following: study skills, digital tools, research, writing and editing strategies, math, professional practices (rà ©sumà ©s, cover letters, documentation), idea generation, project management, organization, and more. For more information, location and hours, please visit the ACE Homeroom site: http://homeroom.pnca.edu/sites/1019 About Your Library The Charles Voorhies Fine Art Library provides research assistance, help with citations and bibliographies and a place to document your artwork. Whether you are looking for articles, books, audio collections, DVDs, or Web resources, the library can help! For research help contact Dan McClure (dmcclure@pnca.edu) and for help with library materials contact Serenity Ibsen (sibsen@pnca.edu). More information is available at www.library.pnca.edu. Statement on Academic Integrity PNCA values intellectual honesty and encourages authentic expression, independent thinking and original writing. The College expects that all work conducted and submitted by our students shall be the combined result of original thought and ethical research. All acts of plagiarism, whether deliberate or unintentional, are considered a violation of the Student Code of Conduct and will not be tolerated on the PNCA campus. It is the student’s responsibility to be aware of and to act in accordance with the PNCA Guidelines for Academic Honesty. This is a document that defines plagiarism, discusses the conventions of ethical research and documentation, and explains the appropriate uses of source materials. These guidelines also describe the student’s responsibility for maintaining documentation and evidence of research in order to verify originality in all writing assignments at PNCA. The document: PNCA Guidelines for Academic Honesty is provided for you in the following locat ions on campus: the Student Handbook, the Library’s Homeroom site, the Academic Integrity HomeRoom site, the ACE HomeRoom site, the Foundation HomeRoom site, the Liberal Arts Homeroom site. You may also view written copies of the PNCA Guidelines for Academic Honesty in the office of Student Services, the Academic Dean’s office, and the PNCA Library. Student Information + Responsibilities Students are expected to have in their possession a current edition of the Student Handbook. Students are responsible for all the information contained in the handbook, and should refer to the handbook frequently for deadlines, policies, procedures, and responsibilities. Student Handbooks are available in the office of Student Services. Students are expected to check their student mailboxes frequently for communications from their instructors or from the administrative offices of the college. Week Two is the last week that you may add or drop a class with no penalty. Week Eight is the last week that you may withdraw from a class with a â€Å"W.† PNCA Grading Criteria This is the institutional grading policy for all PNCA students. Grades are distributed after the end of each semester. Grading Criteria Grade A: Student performance is outstanding. Student exhibits excellent achievement and craftsmanship in all aspects of work. Student exceeds the problem criteria and consistently challenges himself/herself to seek fresh solutions to assigned problems. Student exhibits a commitment to expanding ideas, vocabulary and performance. Student’s attendance, participation and class involvement are excellent. Grade B: Student performs beyond requirements of assignments. Student exhibits above-average progress and craftsmanship in all work. Student meets and exceeds the problem criteria. Student exhibits above-average interest in expanding ideas, vocabulary and performance. Student’s attendance, participation and class involvement are above average. Grade C: Student performance is average and all requirements are fulfilled. Student exhibits an average level of progress and improvement in all work. Student meets the problem criteria. Student exhibits interest in expanding ideas, vocabulary and performance. Student’s attendance, participation and class involvement are adequate. Grade D: Student performance is uneven and requirements are partially fulfilled. Student’s output is minimal. Student exhibits minimal improvement in work. Student does not meet the problem criteria in all assignments. Student exhibits minimal interest in expanding ideas, vocabulary and performance. Student’s attendance, participation and class involvement are less than adequate. Grade F: No credit earned. Student fails to meet a minimum performance level. Student does not exhibit achievement, progress or adequate levels of craftsmanship in all assignments. Student’s work is consistently incomplete or unsuccessful. Student’s attendance, participation and class involvement are inadequate. Pass/Fail Grade: A Pass/Fail grade will be given for designated courses in which the course content is such that direct faculty oversight of the learning experience is not possible, and evaluation on the present grading scale would be difficult. â€Å"Pass† implies a â€Å"C† grade or above. â€Å"Fail† implies less than a â€Å"C† grade and course work graded as â€Å"Fail† does not apply to the degree. Pass/Fail grades are not calculated in the grade point average. This grading applies to Internships. Graphic Design Co-op uses traditional letter grades. Incompletes In certain situations, a student may request an â€Å"Incomplete† grade in a class. You may petition for an â€Å"Incomplete† only if your situation meets both of these conditions: 1. An extenuating circumstance exists and it has prevented you from completing the coursework (Extenuating circumstances are illnesses, family, emergencies, etc.), 2. You are currently in good standing in the class. See the Student Handbook for more information about Grades and Incompletes.